This project focuses on the implementation of a real-time candy vending machine using Verilog Hardware Description Language (HDL). The main objective is to design a digital system that simulates the operation of a candy machine, including accepting coin inputs and monitoring the total inserted amount in real time. Verilog HDL is used to model the system’s behavior at the register– transfer level, making it suitable for academic and conceptual understanding of digital design. The candy machine is designed using sequential logic components, such as registers, counters, and conditional logic, instead of finite state machines or physical hardware implementation. The system continuously adds the value of inserted coins and compares it with a predefined candy cost. When the required amount is reached, the machine generates a candy dispense signal and resets the balance for the next transaction. A reset mechanism is also included to initialize the system and handle incorrect or incomplete inputs. The complete design is verified through simulation, ensuring correct functionality under various input conditions such as insufficient balance, exact payment, and reset operation. This project demonstrates the practical use of Verilog HDL for modeling real-time digital systems without hardware dependency. It provides a strong foundation for understanding vending machine logic, sequential circuit design, and hardware description concepts, which are essential for further studies in digital electronics and VLSI design.

Keywords: VLSI, RTL design, verilog HDL, digital system, FPGA

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1. Sati R, Mishra V, Verma G. Simulation of vending machine design using Verilog HDL. In: 2022 2nd Asian Conference on Innovation in Technology (ASIANCON); 2022 Aug 26; Pune, India. Piscataway (NJ): IEEE; 2022. p. 1–5.
2. Chidananda Datta P, Vinay Kumar C, Singh R, Mummaneni K. Optimized RTL design of a vending machine through FSM using Verilog HDL. In: Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2022. Singapore: Springer Nature Singapore; 2022. p. 305–316.
3. Brown S, Vranesic Z. Digital logic with Verilog design. New York: McGraw-Hill; 2003.
4. Qureshi MA, Aziz A, Rasool HF, Ibrahim M, Ghani U, Abbas H. Design and implementation of vending machine using Verilog HDL. In: 2011 2nd International Conference on Networking and Information Technology (IPCSIT); 2011 Jul. Singapore: IACSIT Press; 2011. Vol. 17.
5. Dawson C, Pattanam SK, Roberts D. The Verilog procedural interface for the Verilog hardware description language. In: Proceedings of IEEE International Verilog HDL Conference; 1996 Feb 26; San Jose, CA, USA. Piscataway (NJ): IEEE; 1996. p. 17–23.
6. Wakerly JF. Digital design: Principles and practices. 4th ed. Noida: Pearson Education India; 2008.
7. Rakshith S, Niranjana S. User-friendly vending machines: A Moore FSM perspective. In: 2024 5th IEEE Global Conference for Advancement in Technology (GCAT); 2024 Oct 4; Bangalore, India. Piscataway (NJ): IEEE; 2024. p. 1–6.
8. Ferdjallah M. Introduction to digital systems: Modeling, synthesis, and simulation using VHDL. Hoboken (NJ): John Wiley & Sons; 2011.
9. Fuad MH, Yeassin R, Hassan KM, Sykot MM, Nayan MF. Design of a vending machine using Verilog HDL and implementation in Genus & Encounter. Eur J Electr Eng Comput Sci. 2023;7(6):88–95.
10. Chidananda Datta P, Vinay Kumar C, Singh R, Mummaneni K. Optimized RTL design of a vending machine through FSM using Verilog HDL. In: Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2022. Singapore: Springer Nature Singapore; 2022. p. 305–316.
11. Singh R, Sai K, Reddy M, Kalyan Y, Pendela R. Design and optimization of FPGA-based vending machine. In: Proceedings of the International Conference on Recent Advances in Artificial Intelligence for Sustainable Development (RAISD 2025); 2025 Jul 17. Singapore: Springer Nature; 2025. p. 77.

This project focuses on the implementation of a real-time candy vending machine using Verilog Hardware Description Language (HDL). The main objective is to design a digital system that simulates the operation of a candy machine, including accepting coin inputs and monitoring the total inserted amount in real time. Verilog HDL is used to model the system’s behavior at the register– transfer level, making it suitable for academic and conceptual understanding of digital design. The candy machine is designed using sequential logic components, such as registers, counters, and conditional logic, instead of finite state machines or physical hardware implementation. The system continuously adds the value of inserted coins and compares it with a predefined candy cost. When the required amount is reached, the machine generates a candy dispense signal and resets the balance for the next transaction. A reset mechanism is also included to initialize the system and handle incorrect or incomplete inputs. The complete design is verified through simulation, ensuring correct functionality under various input conditions such as insufficient balance, exact payment, and reset operation. This project demonstrates the practical use of Verilog HDL for modeling real-time digital systems without hardware dependency. It provides a strong foundation for understanding vending machine logic, sequential circuit design, and hardware description concepts, which are essential for further studies in digital electronics and VLSI design.

Keywords: VLSI, RTL design, verilog HDL, digital system, FPGA

🔒 This is a subscription article

Full text is available to subscribers and institutional members. Please choose an option below to access it.

1. Sati R, Mishra V, Verma G. Simulation of vending machine design using Verilog HDL. In: 2022 2nd Asian Conference on Innovation in Technology (ASIANCON); 2022 Aug 26; Pune, India. Piscataway (NJ): IEEE; 2022. p. 1–5.
2. Chidananda Datta P, Vinay Kumar C, Singh R, Mummaneni K. Optimized RTL design of a vending machine through FSM using Verilog HDL. In: Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2022. Singapore: Springer Nature Singapore; 2022. p. 305–316.
3. Brown S, Vranesic Z. Digital logic with Verilog design. New York: McGraw-Hill; 2003.
4. Qureshi MA, Aziz A, Rasool HF, Ibrahim M, Ghani U, Abbas H. Design and implementation of vending machine using Verilog HDL. In: 2011 2nd International Conference on Networking and Information Technology (IPCSIT); 2011 Jul. Singapore: IACSIT Press; 2011. Vol. 17.
5. Dawson C, Pattanam SK, Roberts D. The Verilog procedural interface for the Verilog hardware description language. In: Proceedings of IEEE International Verilog HDL Conference; 1996 Feb 26; San Jose, CA, USA. Piscataway (NJ): IEEE; 1996. p. 17–23.
6. Wakerly JF. Digital design: Principles and practices. 4th ed. Noida: Pearson Education India; 2008.
7. Rakshith S, Niranjana S. User-friendly vending machines: A Moore FSM perspective. In: 2024 5th IEEE Global Conference for Advancement in Technology (GCAT); 2024 Oct 4; Bangalore, India. Piscataway (NJ): IEEE; 2024. p. 1–6.
8. Ferdjallah M. Introduction to digital systems: Modeling, synthesis, and simulation using VHDL. Hoboken (NJ): John Wiley & Sons; 2011.
9. Fuad MH, Yeassin R, Hassan KM, Sykot MM, Nayan MF. Design of a vending machine using Verilog HDL and implementation in Genus & Encounter. Eur J Electr Eng Comput Sci. 2023;7(6):88–95.
10. Chidananda Datta P, Vinay Kumar C, Singh R, Mummaneni K. Optimized RTL design of a vending machine through FSM using Verilog HDL. In: Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2022. Singapore: Springer Nature Singapore; 2022. p. 305–316.
11. Singh R, Sai K, Reddy M, Kalyan Y, Pendela R. Design and optimization of FPGA-based vending machine. In: Proceedings of the International Conference on Recent Advances in Artificial Intelligence for Sustainable Development (RAISD 2025); 2025 Jul 17. Singapore: Springer Nature; 2025. p. 77.