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Design and Implementation of 32-Bit High Speed Vedic MultiplierBy R Vinodini Sri, M Mohammad Sadaq, P Sai Varshika, R Durga Anusha, O Lalitha Bhavani, Akula Pravin, I Rama Satya Nageswara Rao
Abstract: To accomplish quicker and more effective calculation, this project combines a Kogge-Stone Adder with the Vedic Urdhva Tiryagbhyam (vertical and crosswise) multiplication method to create a high-speed 32-bit binary multiplier. The KoggeStone Adder minimizes total latency by reducing carry delay at the final addition stage, while the Vedic algorithm allows partial products to be formed simultaneously, increasing speed. This architecture divides 32-bit values into smaller components, multiplies them in parallel, …
Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 12, Issue 1, 2026 · pp. 18–26 Read article →