International Journal of Digital Communication and Analog Signals
Efficient Implementation of the AES Using FPGA
Abstract
Rijndael encryption, developed by Joan Daemen and Vincent Rijmen and recently designated as the official Advanced Encryption Standard (AES), is well suited for hardware use.A few articles discuss the practical structures of ASIC and FPGA (FPGAs). This study proposes an effective way to integrate Rijndael encryption and encoding into a single FPGA architecture with minimal space constraints. The proposed project is equivalent to the smallest Xilinx FPGA, manages 208 Mbps data transmission, uses 163 pieces and three blocks of RAM, and exceeds similarly well-known designs by 68 percent according to the Phryput / Area rating. This paper also includes coarisons with other FPGA families' DES, tripleDES, and AES implementations (such as the Xilinx Virtex-II).References (42)
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- ISSN: 2455-0329
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