Design and Implementation of BIST Using VERILOG HDL

Abhishek Sharma

Abstract

Very large scale integration has had a significant impact in a very short span of time on the growth of integrated circuit technology. It has reduced the size and, more importantly, the cost, it increases the circuit complexity. However, there are potential issues that may delay the effective use and growth of future VLSI technology. Among these is the issue of circuit testing, which is becoming increasingly difficult as the integration scale increases. Due to the high number of circuits and limited input/output access characterizing VLSI circuits, conventional test approaches are often ineffective and insufficient for VLSI circuits. The standard linear feedback shift register (LFSR) used to generate patterns can give repetitive patterns that are not efficient for complete test coverage in some cases. The primitive polynomial-based LFSR generates pseudo-random pattern generator (PRPG) of maximum length. Built-in self-test (BIST) is used as a technique of design allowing the testing of a circuit itself. BIST has gained popularity as an effective solution to the costs of circuit testing, quality testing and problems of test reuse. Keywords: linear feedback shift register (LFSR), pseudo random pattern generator (PRPG), multiple input signature register (MISR), circuit under test (CUT), read-only memory (ROM)

Design and Implementation of BIST Using VERILOG HDL

Abstract

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