Poornima H S, Nagaraju C | International Journal of Microelectronics and Digital integrated circuits | Vol 11, Issue 01 | pp. 0 | ISSN: 2456-3986
Abstract
Flash storage technology, omnipresent in modern electronics and computer systems, relies on page-based data storage. However, reading these pages at distinct clock times during various cycles presents latency issues that hamper flash storage device performance. The conventional use of asynchronous clock pulses for page reading results in the Clock Domain Crossing (CDC) challenges in design verification, complicating the setup and holding time violation for statistical timing analysis in physical design and leads to power consumption and complexity in fabrication. This research aims for generating clock pulse using PLL included PLA synchronous clock for Flash memory and Multi pair technique for reading pages of the flash memory to reduce latency in reading and writing the flash memory and increasing optimization with improve in power performance and wear leveling of the flash memory.
Keywords: Flash memory, Latency reduction, Synchronous clock, Phase-Locked Loop, Clock domain crossing.
Keywords
Phase-Locked Loop, Synchronous clock, Flash memory, Latency reduction
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How to cite this article
@article{SPH2025,
author = {Poornima H S and Nagaraju C},
title = {Accelerating Flash Memory Efficiency using Phase Lock Loop driven Programmable Logic Array},
journal = {International Journal of Microelectronics and Digital integrated circuits},
year = {2025},
volume = {11},
number = {01},
pages = {0},
issn = {2456-3986},
url = {https://journalspub.com/publication/ijmdic/article=15915}
}