This work presents the design, construction, and experimental evaluation of a 1-bit Arithmetic Logic Unit (ALU) implemented entirely with operational amplifiers (op-amps), using only LM324 devices, passive components, and a dual-polarity ±12 V supply on a breadboard prototype. The ALU per- forms eight fundamental arithmetic and logic operations, addition, subtraction, AND, OR, NOT, NAND, NOR, and XOR, by combining op-amp comparator-mode logic gates with op-amp-based summing and difference amplifiers for arithmetic, a 2-to-4 line decoder for operation selection, and an analog AND- gated multiplexer for contention-free output routing. Design-level considerations, including reference- threshold placement, resistor-tolerance effects on comparator switching points, and the sign-restoring comparator stage that couples the linear arithmetic block to the saturated logic-level output bus, are described alongside the circuit topology of each module. Every logic gate and the decoder were ver- ified experimentally against their expected truth tables using a digital multimeter and an oscilloscope, with logic HIGH and LOW consistently measured near +10 to +11 V and −10 to −11 V respectively across all eight input combinations tested; small (1–2 V) gate-to-gate variations in the saturated output levels were observed and attributed to resistor tolerance and cascaded-stage offsets rather than to logic errors. The results confirm that comparator-mode and linear op-amp configurations can be combined reliably to realize both Boolean and arithmetic truth tables, and the completed hardware is positioned, with reference to prior work on comparator design, low-power op-amp design, and reconfigurable teach- ing platforms, as a low-cost, physically verifiable platform for studying the voltage-threshold boundary between analog and digital circuit design.

Keywords - Operational amplifiers, arithmetic logic unit, comparator, logic gates, decoder, multiplexer

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1. HU Z. APPLICATIONS OF OP-AMP IN AUTOMATIC CIRCUIT DESIGN. APPLIED AND COMPUTATIONAL ENGINEERING Учредители: EWA Publishing. 2025;126(1):169-75.
2. Labonnah FR, Reaz MB, Yin CC, Marufuzzaman M, Rahman MA. A high-speed and low-offset dynamic latch comparator. The Scientific World Journal. 2014;2014.
3. Sharma D, Nath V. CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation. Results in Engineering. 2024 Jun 1;22:102357.
4. Mistry C, Bose R, Basak A. An Architecture for High-Gain Multistage CMOS Amplifiers: A Review. Nanoscale Devices. 2026:143-67.
5. Mukti IZ, Khan ER, Biswas KK. 1.8-V Low Power, High-Resolution, High-Speed Comparator With Low Offset Voltage Implemented in 45nm CMOS Technology. Journal of VLSI circuits and systems. 2024;6(1):19-24.
6. Papanikolaou CP, Tombras GS, Van De Bogart KL, Stetzer MR. Investigating student understanding of operational-amplifier circuits. American Journal of Physics. 2015 Dec 1;83(12):1039-50.
7. Chong PL, Ganesan S, Ng PK, Kong FY. A TRIZ-Adopted development of a compact experimental board for the teaching and learning of operational amplifier with multiple circuit configurations. Sustainability. 2022 Oct 29;14(21):14115.
8. Costa R, Portela P, Alves GR, Felgueiras MC, Viegas C. An alternative way of teaching Operational Amplifiers using a reconfigurable and expandable kit. IEEE Revista Iberoamericana de Tecnologias del Aprendizaje. 2021 Nov 8;16(3):307-17.
9. Chakraborty S, Pandey A, Nath V. A highly linear and high gain operational amplifier. InIEEE International conference on electrical, electronics, signal, communication and optimization (EESCO-2015) organized by Vignan’s Institute of Information Technology 2015 Jan 24 (pp. 24- 25).
10. Zhang K, Cui X, Cui X. A design of high performance full adder with memristors. In2017 IEEE 12th International Conference on ASIC (ASICON) 2017 Oct 25 (pp. 746-479). IEEE.
11. Chevella S, O’Hare D, O’Connell I. A low-power 1-V supply dynamic comparator. IEEE Solid- State Circuits Letters. 2020 Jul 15;3:154-7.
12. Thai HH, Pham CK, Le DH. Design of a low-power and low-area 8-bit flash ADC using a double-tail comparator on 180 nm CMOS process. Sensors. 2022 Dec 21;23(1):76.
13. Baruah RK. Design of a low power low voltage CMOS opamp. arXiv preprint arXiv:1003.5439. 2010 Mar 29.
14. Abrar MM. Design and implementation of schmitt trigger using operational amplifier. International Journal of Engineering Research and Applications. 2017 Jan;7(1):5-9.
15. Akshata S, Arpitha E, Deepashree VA, Pushpa LN. Low power comparator design using reversible logic gates–adiabatic circuits. International journal of engineering research & technology. 2018;6(13).
16. Rivadeneyra A, Romero FJ, Haider M, Bhatt VD, Salmeron JF, Rodriguez N, Morales DP, Becherer M. Reconfigurable electronic platforms: A top-down approach to learn about design and integration of electronic systems. Micromachines. 2022 Mar 15;13(3):442.
17. Maan AK, James AP. Voltage controlled memristor threshold logic gates. In2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2016 Oct 25 (pp. 376-379). IEEE.
18. Zahoor F, Hussin FA, Khanday FA, Ahmad MR, Mohd Nawi I. Ternary arithmetic logic unit design utilizing carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM). Micromachines. 2021 Oct 21;12(11):1288..
19. Shinde JR, Sharma S, Dash L. An optimization design approach for arithmetic logic unit. InInternational Conference on Intelligent Computing and Communication Technologies 2019 Jan 9 (pp. 707-716). Singapore: Springer Singapore.
20. Rekha P, Shirur YJ, Shamanth KS, Gowda KP, Bindu S. Full-Swing Gate Diffusion Input Based 32-Bit Arithmetic and Logic Unit: Design, Implementation, and Comparative Analysis. Journal of VLSI Circuits and Systems. 2026 Jun 15;8(1):69-80.

This work presents the design, construction, and experimental evaluation of a 1-bit Arithmetic Logic Unit (ALU) implemented entirely with operational amplifiers (op-amps), using only LM324 devices, passive components, and a dual-polarity ±12 V supply on a breadboard prototype. The ALU per- forms eight fundamental arithmetic and logic operations, addition, subtraction, AND, OR, NOT, NAND, NOR, and XOR, by combining op-amp comparator-mode logic gates with op-amp-based summing and difference amplifiers for arithmetic, a 2-to-4 line decoder for operation selection, and an analog AND- gated multiplexer for contention-free output routing. Design-level considerations, including reference- threshold placement, resistor-tolerance effects on comparator switching points, and the sign-restoring comparator stage that couples the linear arithmetic block to the saturated logic-level output bus, are described alongside the circuit topology of each module. Every logic gate and the decoder were ver- ified experimentally against their expected truth tables using a digital multimeter and an oscilloscope, with logic HIGH and LOW consistently measured near +10 to +11 V and −10 to −11 V respectively across all eight input combinations tested; small (1–2 V) gate-to-gate variations in the saturated output levels were observed and attributed to resistor tolerance and cascaded-stage offsets rather than to logic errors. The results confirm that comparator-mode and linear op-amp configurations can be combined reliably to realize both Boolean and arithmetic truth tables, and the completed hardware is positioned, with reference to prior work on comparator design, low-power op-amp design, and reconfigurable teach- ing platforms, as a low-cost, physically verifiable platform for studying the voltage-threshold boundary between analog and digital circuit design.

Keywords - Operational amplifiers, arithmetic logic unit, comparator, logic gates, decoder, multiplexer

🔒 This is a subscription article

Full text is available to subscribers and institutional members. Please choose an option below to access it.

1. HU Z. APPLICATIONS OF OP-AMP IN AUTOMATIC CIRCUIT DESIGN. APPLIED AND COMPUTATIONAL ENGINEERING Учредители: EWA Publishing. 2025;126(1):169-75.
2. Labonnah FR, Reaz MB, Yin CC, Marufuzzaman M, Rahman MA. A high-speed and low-offset dynamic latch comparator. The Scientific World Journal. 2014;2014.
3. Sharma D, Nath V. CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation. Results in Engineering. 2024 Jun 1;22:102357.
4. Mistry C, Bose R, Basak A. An Architecture for High-Gain Multistage CMOS Amplifiers: A Review. Nanoscale Devices. 2026:143-67.
5. Mukti IZ, Khan ER, Biswas KK. 1.8-V Low Power, High-Resolution, High-Speed Comparator With Low Offset Voltage Implemented in 45nm CMOS Technology. Journal of VLSI circuits and systems. 2024;6(1):19-24.
6. Papanikolaou CP, Tombras GS, Van De Bogart KL, Stetzer MR. Investigating student understanding of operational-amplifier circuits. American Journal of Physics. 2015 Dec 1;83(12):1039-50.
7. Chong PL, Ganesan S, Ng PK, Kong FY. A TRIZ-Adopted development of a compact experimental board for the teaching and learning of operational amplifier with multiple circuit configurations. Sustainability. 2022 Oct 29;14(21):14115.
8. Costa R, Portela P, Alves GR, Felgueiras MC, Viegas C. An alternative way of teaching Operational Amplifiers using a reconfigurable and expandable kit. IEEE Revista Iberoamericana de Tecnologias del Aprendizaje. 2021 Nov 8;16(3):307-17.
9. Chakraborty S, Pandey A, Nath V. A highly linear and high gain operational amplifier. InIEEE International conference on electrical, electronics, signal, communication and optimization (EESCO-2015) organized by Vignan’s Institute of Information Technology 2015 Jan 24 (pp. 24- 25).
10. Zhang K, Cui X, Cui X. A design of high performance full adder with memristors. In2017 IEEE 12th International Conference on ASIC (ASICON) 2017 Oct 25 (pp. 746-479). IEEE.
11. Chevella S, O’Hare D, O’Connell I. A low-power 1-V supply dynamic comparator. IEEE Solid- State Circuits Letters. 2020 Jul 15;3:154-7.
12. Thai HH, Pham CK, Le DH. Design of a low-power and low-area 8-bit flash ADC using a double-tail comparator on 180 nm CMOS process. Sensors. 2022 Dec 21;23(1):76.
13. Baruah RK. Design of a low power low voltage CMOS opamp. arXiv preprint arXiv:1003.5439. 2010 Mar 29.
14. Abrar MM. Design and implementation of schmitt trigger using operational amplifier. International Journal of Engineering Research and Applications. 2017 Jan;7(1):5-9.
15. Akshata S, Arpitha E, Deepashree VA, Pushpa LN. Low power comparator design using reversible logic gates–adiabatic circuits. International journal of engineering research & technology. 2018;6(13).
16. Rivadeneyra A, Romero FJ, Haider M, Bhatt VD, Salmeron JF, Rodriguez N, Morales DP, Becherer M. Reconfigurable electronic platforms: A top-down approach to learn about design and integration of electronic systems. Micromachines. 2022 Mar 15;13(3):442.
17. Maan AK, James AP. Voltage controlled memristor threshold logic gates. In2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2016 Oct 25 (pp. 376-379). IEEE.
18. Zahoor F, Hussin FA, Khanday FA, Ahmad MR, Mohd Nawi I. Ternary arithmetic logic unit design utilizing carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM). Micromachines. 2021 Oct 21;12(11):1288..
19. Shinde JR, Sharma S, Dash L. An optimization design approach for arithmetic logic unit. InInternational Conference on Intelligent Computing and Communication Technologies 2019 Jan 9 (pp. 707-716). Singapore: Springer Singapore.
20. Rekha P, Shirur YJ, Shamanth KS, Gowda KP, Bindu S. Full-Swing Gate Diffusion Input Based 32-Bit Arithmetic and Logic Unit: Design, Implementation, and Comparative Analysis. Journal of VLSI Circuits and Systems. 2026 Jun 15;8(1):69-80.