2 publications

• Published Subscription 29 Jul 2019

  High-Performance FinFET Based 8T SRAM with Enhanced Performance Parameters Using Self-Controllable Voltage level (SVL) Technique

  By Nikhil Saxena, Vaibhav Shrivastava

  Abstract: The scaling of standard single-gate bulk CMOS faces great challenge in the nanometer regime due to the severe short-channel effects (SCE) which causes significant increase in the leakage current. In this paper, a high-performance eight transistor (8T) SRAM has been proposed for reduction in leakage current and power consumption using double-gate FinFET with the proposed technique. Double gate FinFET has better SCEs performance compared to conventional CMOS. In this paper, …

  Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 5, Issue 1, 2019 · pp. 16–24 Read article →

• Published Subscription 29 Jul 2019

  Reduction of Leakage Parameters in Novel 6CNT Schmitt Trigger Using LECTOR Technique

  By Nikhil Saxena, Divyanshi Ahuja, Sudeepti Shukla, Shivam Gangil, Ankita Shoorkar

  Abstract: This paper presents an overview of design optimization of leakage parameters in 6CNT Schmitt trigger using proposed power reduction technique. We use lector technique to reduce leakage parameter in the circuit. The simulation has been performed using H-spice software at 32nm technology. Schmitt trigger is used to convert analog signals to digital signals, i.e., it converts any kind of wave at input to square wave at output. Power Dissipation and …

  Published in International Journal of Microelectronics and Digital integrated circuits · Vol. 5, Issue 1, 2019 · pp. 36–42 Read article →