Accelerating Flash Memory Efficiency using Phase Lock Loop driven Programmable Logic Array

Volume: 11 | Issue: 01 | Year 2025 | Subscription
International Journal of Microelectronics and Digital integrated circuits
Received Date: 01/18/2018
Acceptance Date: 02/24/2024
Published On: 2025-04-02
First Page: 0
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https://doi.org/10.37628/ijmdic.v11i01.15915

By: Poornima H S and Nagaraju C

1-Assistant Professor, Department of AI & ML, RNS Institute of Technology, Visvesvaraya Technological University, Rajarajeshwari Nagar, Bengaluru, Karnataka
2-Assistant Professor, Department of Electronics and Communication Engineering, National Institute of Education, Visvesvaraya Technological University, Mysuru, Karnataka, India

Abstract

Flash storage technology, omnipresent in modern electronics and computer systems, relies on page-based data storage. However, reading these pages at distinct clock times during various cycles presents latency issues that hamper flash storage device performance. The conventional use of asynchronous clock pulses for page reading results in the Clock Domain Crossing (CDC) challenges in design verification, complicating the setup and holding time violation for statistical timing analysis in physical design and leads to power consumption and complexity in fabrication. This research aims for generating clock pulse using PLL included PLA synchronous clock for Flash memory and Multi pair technique for reading pages of the flash memory to reduce latency in reading and writing the flash memory and increasing optimization with improve in power performance and wear leveling of the flash memory.

Keywords: Flash memory, Latency reduction, Synchronous clock, Phase-Locked Loop, Clock domain crossing.

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Citation:

How to cite this article: Poornima H S and Nagaraju C, Accelerating Flash Memory Efficiency using Phase Lock Loop driven Programmable Logic Array. International Journal of Microelectronics and Digital integrated circuits. 2025; 11(01): 0-p.

How to cite this URL: Poornima H S and Nagaraju C, Accelerating Flash Memory Efficiency using Phase Lock Loop driven Programmable Logic Array. International Journal of Microelectronics and Digital integrated circuits. 2025; 11(01): 0-p. Available from:https://journalspub.com/publication/ijmdic/article=15915

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https://doi.org/10.37628/ijmdic.v11i01.15915
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