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By: R Vinodini Sri, M Mohammad Sadaq, P Sai Varshika, R Durga Anusha, O Lalitha Bhavani, Akula Pravin, and I Rama Satya Nageswara Rao.
1,2,3,4,5. UG Scholar ,Dept. of ECE, Bonam Venkata Chalamayya Engineering College(A),Odalarevu, Andhra Pradesh, India
6. Professor ,Dept. of ECE, Bonam Venkata Chalamayya Engineering College(A),Odalarevu, Andhra Pradesh, India
7. Assistant Professor,Dept. of ECE, Bonam Venkata Chalamayya Engineering College(A),Odalarevu, Andhra Pradesh, India
To accomplish quicker and more effective calculation, this project combines a Kogge-Stone Adder with the Vedic Urdhva Tiryagbhyam (vertical and crosswise) multiplication method to create a high-speed 32-bit binary multiplier. The KoggeStone Adder minimizes total latency by reducing carry delay at the final addition stage, while the Vedic algorithm allows partial products to be formed simultaneously, increasing speed. This architecture divides 32-bit values into smaller components, multiplies them in parallel, and then combines the results. Usually, Verilog or VHDL are used to construct the multiplier, which may be emulated using programs like FPGA systems like Xilinx were used to develop AMD Vivado. The design focuses on scalability and modularity, facilitating easy extension to higher bit-width multipliers with minimal performance degradation. It is designed with an emphasis on optimizing area efficiency and power consumption, which makes it appropriate for contemporary low-power VLSI systems. Moreover, a comparative analysis with traditional multipliers shows enhanced speed and diminished delay, confirming the efficacy of the suggested method. This optimized VLSI architecture is ideal for time-sensitive and power-sensitive applications such as digital signal processing (DSP), image processing, processors, and other real-time computing systems that need quick arithmetic operations due to its high speed, straightforward structure, low delay, and effective hardware utilization.
Keywords – 32-bit Vedic Multiplier, Urdhva Tiryagbhyam, Carry Save Adder (CSA), High- Speed VLSI Design, FPGA Implementation
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