To accomplish quicker and more effective calculation, this project combines a Kogge-Stone Adder with the Vedic Urdhva Tiryagbhyam (vertical and crosswise) multiplication method to create a high-speed 32-bit binary multiplier. The KoggeStone Adder minimizes total latency by reducing carry delay at the final addition stage, while the Vedic algorithm allows partial products to be formed simultaneously, increasing speed. This architecture divides 32-bit values into smaller components, multiplies them in parallel, and then combines the results. Usually, Verilog or VHDL are used to construct the multiplier, which may be emulated using programs like FPGA systems like Xilinx were used to develop AMD Vivado. The design focuses on scalability and modularity, facilitating easy extension to higher bit-width multipliers with minimal performance degradation. It is designed with an emphasis on optimizing area efficiency and power consumption, which makes it appropriate for contemporary low-power VLSI systems. Moreover, a comparative analysis with traditional multipliers shows enhanced speed and diminished delay, confirming the efficacy of the suggested method. This optimized VLSI architecture is ideal for time-sensitive and power-sensitive applications such as digital signal processing (DSP), image processing, processors, and other real-time computing systems that need quick arithmetic operations due to its high speed, straightforward structure, low delay, and effective hardware utilization.

Keywords - 32-bit Vedic Multiplier, Urdhva Tiryagbhyam, Carry Save Adder (CSA), High- Speed VLSI Design, FPGA Implementation

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1. Akhter S. VHDL implementation of fast NxN multiplier based on vedic mathematic. In2007 18th European Conference on Circuit Theory and Design 2007 Aug 27 (pp. 472-475). IEEE.
2. Ngaraj S, Reddy GS, Mastani SA. A Comparative Study on Different Multipliers–Survey. Journal of Advanced Research in Dynamical and Control Systems. 2018;14:739-52.
3. Pushpa M, Nagaraj S. Design and Analysis of 8-bit Array Carry Save Array Braun Wallace Tree and Vedic Multipliers. InIEEE Sponsored International Conference On New Trends In Engineering & Technology (ICNTET 2018) 2018.
4. Nagaraj S, Thyagarajan K, Srihari D, Gopi K. Design and analysis of Wallace tree multiplier for CMOS and CPL logic. In2018 International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC) 2018 Mar 28 (pp. 006-010). IEEE.
5. Thomas J, Pushpangadan R, Jinesh S. Comparative study of performance vedic multiplier on the basis of adders used. In2015 IEEE international WIE conference on electrical and computer engineering (WIECON-ECE) 2015 Dec 19 (pp. 325-328). IEEE.
6. Karunakaran S. High Performance VLSI Architecture of Multiplexer and Demultiplexer Using Various Adiabatic Logic. In2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE) 2021 Dec 16 (pp. 1-4). IEEE.
7. Nagaraj S, Reddy KV, Kumar PA. Analysis of Vedic Multiplier for Conventional CMOS and Complementary Pass Transistor Logic (CPL) Logics. SAMRIDDHI: A Journal of Physical Sciences, Engineering and Technology. 2020 Nov 30;12(SUP 3):94-8.
8. Au LS, Burgess N. A (4: 2) adder for unified GF (p) and GF (2 n) Galois field multipliers. InConference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002. 2002 Nov 3 (Vol. 2, pp. 1619- 1623). IEEE.
9. Chittibabu A, Sola VK, Raj CP. ASIC Implementation of New Architecture for constant coefficient Dadda multiplier for High-Speed DSP applications. InProceedings of the National Conference on Recent trends in Electrical, Electronics and Computer Engineering, JCECON 2006 (pp. 299-304).
10. Kumar GG, Charishma V. Design of high speed vedic multiplier using vedic mathematics techniques. International Journal of Scientific and Research Publications. 2012 Mar;2(3):1.
11. Sharma R, Kaur M, Singh G. Design and FPGA implementation of optimized 32-bit Vedic multiplier and square architectures. In2015 International Conference on Industrial Instrumentation and Control (ICIC) 2015 May 28 (pp. 960-964). IEEE.
12. Rao IR, Krishna BM, Shameem S, Khan H, Madhumati GL. Wireless secured data transmission using cryptographic techniques through fpga. International Journal of Engineering and Technology (IJET), e-ISSN. 2016:0975-4024.
13. Prasanna Kumar G, Budumuru PR, Krishna Chaitanya Varma A, Satyanarayana BV, Saran Kumar T, Rao IR. Design Analysis of Memristor-Based 7T SRAM Using Heterojunction Tunneling Transistors. Journal of Circuits, Systems and Computers. 2025 Nov 30;34(17):2550280.
14. Kumar TS, Siddani DP, Rao IR, Harika P, Vijjapu A, Kumar GP, Satyanarayana BV. Low power adder circuit design and implementation using LECTOR technique. InInternational Conference on Cognitive Computing and Cyber Physical Systems 2024 Apr 4 (pp. 159-170). Cham: Springer Nature Switzerland.

To accomplish quicker and more effective calculation, this project combines a Kogge-Stone Adder with the Vedic Urdhva Tiryagbhyam (vertical and crosswise) multiplication method to create a high-speed 32-bit binary multiplier. The KoggeStone Adder minimizes total latency by reducing carry delay at the final addition stage, while the Vedic algorithm allows partial products to be formed simultaneously, increasing speed. This architecture divides 32-bit values into smaller components, multiplies them in parallel, and then combines the results. Usually, Verilog or VHDL are used to construct the multiplier, which may be emulated using programs like FPGA systems like Xilinx were used to develop AMD Vivado. The design focuses on scalability and modularity, facilitating easy extension to higher bit-width multipliers with minimal performance degradation. It is designed with an emphasis on optimizing area efficiency and power consumption, which makes it appropriate for contemporary low-power VLSI systems. Moreover, a comparative analysis with traditional multipliers shows enhanced speed and diminished delay, confirming the efficacy of the suggested method. This optimized VLSI architecture is ideal for time-sensitive and power-sensitive applications such as digital signal processing (DSP), image processing, processors, and other real-time computing systems that need quick arithmetic operations due to its high speed, straightforward structure, low delay, and effective hardware utilization.

Keywords - 32-bit Vedic Multiplier, Urdhva Tiryagbhyam, Carry Save Adder (CSA), High- Speed VLSI Design, FPGA Implementation

🔒 This is a subscription article

Full text is available to subscribers and institutional members. Please choose an option below to access it.

1. Akhter S. VHDL implementation of fast NxN multiplier based on vedic mathematic. In2007 18th European Conference on Circuit Theory and Design 2007 Aug 27 (pp. 472-475). IEEE.
2. Ngaraj S, Reddy GS, Mastani SA. A Comparative Study on Different Multipliers–Survey. Journal of Advanced Research in Dynamical and Control Systems. 2018;14:739-52.
3. Pushpa M, Nagaraj S. Design and Analysis of 8-bit Array Carry Save Array Braun Wallace Tree and Vedic Multipliers. InIEEE Sponsored International Conference On New Trends In Engineering & Technology (ICNTET 2018) 2018.
4. Nagaraj S, Thyagarajan K, Srihari D, Gopi K. Design and analysis of Wallace tree multiplier for CMOS and CPL logic. In2018 International Conference on Computation of Power, Energy, Information and Communication (ICCPEIC) 2018 Mar 28 (pp. 006-010). IEEE.
5. Thomas J, Pushpangadan R, Jinesh S. Comparative study of performance vedic multiplier on the basis of adders used. In2015 IEEE international WIE conference on electrical and computer engineering (WIECON-ECE) 2015 Dec 19 (pp. 325-328). IEEE.
6. Karunakaran S. High Performance VLSI Architecture of Multiplexer and Demultiplexer Using Various Adiabatic Logic. In2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE) 2021 Dec 16 (pp. 1-4). IEEE.
7. Nagaraj S, Reddy KV, Kumar PA. Analysis of Vedic Multiplier for Conventional CMOS and Complementary Pass Transistor Logic (CPL) Logics. SAMRIDDHI: A Journal of Physical Sciences, Engineering and Technology. 2020 Nov 30;12(SUP 3):94-8.
8. Au LS, Burgess N. A (4: 2) adder for unified GF (p) and GF (2 n) Galois field multipliers. InConference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002. 2002 Nov 3 (Vol. 2, pp. 1619- 1623). IEEE.
9. Chittibabu A, Sola VK, Raj CP. ASIC Implementation of New Architecture for constant coefficient Dadda multiplier for High-Speed DSP applications. InProceedings of the National Conference on Recent trends in Electrical, Electronics and Computer Engineering, JCECON 2006 (pp. 299-304).
10. Kumar GG, Charishma V. Design of high speed vedic multiplier using vedic mathematics techniques. International Journal of Scientific and Research Publications. 2012 Mar;2(3):1.
11. Sharma R, Kaur M, Singh G. Design and FPGA implementation of optimized 32-bit Vedic multiplier and square architectures. In2015 International Conference on Industrial Instrumentation and Control (ICIC) 2015 May 28 (pp. 960-964). IEEE.
12. Rao IR, Krishna BM, Shameem S, Khan H, Madhumati GL. Wireless secured data transmission using cryptographic techniques through fpga. International Journal of Engineering and Technology (IJET), e-ISSN. 2016:0975-4024.
13. Prasanna Kumar G, Budumuru PR, Krishna Chaitanya Varma A, Satyanarayana BV, Saran Kumar T, Rao IR. Design Analysis of Memristor-Based 7T SRAM Using Heterojunction Tunneling Transistors. Journal of Circuits, Systems and Computers. 2025 Nov 30;34(17):2550280.
14. Kumar TS, Siddani DP, Rao IR, Harika P, Vijjapu A, Kumar GP, Satyanarayana BV. Low power adder circuit design and implementation using LECTOR technique. InInternational Conference on Cognitive Computing and Cyber Physical Systems 2024 Apr 4 (pp. 159-170). Cham: Springer Nature Switzerland.